Infrastructure for Evaluating
Novel HW/OS Interfaces

To stress-test the virtual memory system, computer architecture researchers are combining standard benchmark programs with synthetically generated inputs that induce large memory footprints. However, for these workloads the relationship between memory footprint and address translation overhead is poorly understood. Using hardware event counters, we characterize the performance of the Intel Haswell microarchitecture MMU across a range of benchmarks, memory footprints, and page sizes. We analyze these measurements using our Walk Cycles Per Instruction (WCPI) framework, which attributes address translation overhead to the program, TLB, MMU cache, and hardware page table walker. We find that address translation overhead often scales with the logarithm of memory footprint, with large pages increasing the footprint at which overhead becomes significant, and that up to 57% of all page table walks are either aborted or lie on the wrong path of speculative execution.

Memory in data centers has run into a scaling problem. With the unrelenting increase in memory capacity, virtual memory does not scale and causes frequent stalls in the processor. On the other hand, the cost of DRAM has skyrocketed as capacity increases, and DRAM now constitutes around half the server TCO in data centers. This talk presents LVM (MICRO '25), which introduces a learning-based approach to the page tables that drastically reduces the cost of page walks, followed by learnings and insights from ongoing work on CXL-attached memory that enables tiered memory in multi-tenant and multi-tier environments, lowering the cost of DRAM in data centers.

Address translation is a performance bottleneck in data-intensive workloads due to large datasets and irregular access patterns that lead to frequent high-latency page table walks (PTWs). We present Victima, a new software-transparent mechanism that drastically increases the translation reach of the processor by leveraging the underutilized resources of the cache hierarchy. The key idea of Victima is to repurpose L2 cache blocks to store clusters of TLB entries, thereby providing an additional low-latency and high-capacity component that backs up the last-level TLB and thus reduces PTWs. Victima has two main components: a PTW cost predictor that identifies costly-to-translate addresses, and a TLB-aware cache replacement policy that prioritizes keeping TLB entries in the cache hierarchy. In native (virtualized) execution environments, Victima improves average end-to-end application performance by 7.4% (28.7%) over the baseline four-level radix-tree-based page table design, is completely transparent to application and system software, and incurs very small area and power overheads.

Modern processors make thousands of fine-grained decisions about memory every microsecond, guided by implicit, hardware-only models. For modern data center applications, these isolated hardware mechanisms leave significant performance on the table. Data center applications are heavily memory-intensive and frequently backend-bound, with a substantial fraction of stalls arising from load operations that access the same cache line but are executed independently. I-Fuse is a profile-guided and speculative load micro-op pair fusion mechanism that rethinks the traditional interface between software and microarchitecture. It combines Profile-Guided Fusion, which identifies high-confidence fusible load pairs using dynamic execution characteristics, with Speculative Fusion, which predicts and reserves resources for a partner micro-op early. Across backend-bound data center applications, I-Fuse achieves substantial IPC improvements and significantly outperforms prior hardware-only approaches.

As the ever-increasing memory footprints of modern workloads strain virtual memory hardware, address translation has become a critical performance bottleneck. Modern architectures, such as ARMv8-A and RISC-V, support OS-assisted TLB coalescing to help alleviate this overhead, yet OS support remains lacking. This talk presents Elastic Translations, a hardware-tailored OS memory management framework that enables the OS to effectively and efficiently drive TLB coalescing hardware to tame the address translation overhead.

Hardware-software cooperative techniques are powerful approaches to improve the performance, quality of service, and security of general-purpose processors. They are however typically challenging to rapidly implement and evaluate in real hardware as they require full-stack changes to the hardware, OS, system software, and ISA. MetaSys is the first open-source FPGA-based infrastructure, with a prototype in a RISC-V core, to enable the rapid implementation and evaluation of a wide range of cross-layer techniques in real hardware. MetaSys implements a rich hardware-software interface and lightweight metadata support that can be used as a common basis to rapidly implement and evaluate new cross-layer techniques. We demonstrate MetaSys's versatility by implementing three cross-layer techniques for prefetching, bounds checking, and return address protection, each requiring only ~100 lines of Chisel code.