📄️ Baseline MMU
This document provides an in-depth walkthrough of the Memory Management Unit (MMU) implementation.
📄️ Part-of-Memory TLB (POM-TLB) MMU Design
In this section, we will discuss the implementation of the Part-of-Memory TLB (POM-TLB) MMU design. The POM-TLB design is a software-managed TLB that uses a software-managed L3 TLB to reduce the overhead of address translation. The POM-TLB design is based on the work by Papadopoulou et al..
📄️ Range Mappings MMU Design
In this section, we will discuss the implementation of the Range Mappings MMU design. The Range Mappings MMU design is based on the work by
📄️ Page Table Walker
The page table walker (PTW) is a critical component of the memory management unit (MMU) that translates virtual addresses to physical addresses. The PTW is responsible for walking the page table hierarchy to find the physical address corresponding to a given virtual address. This process involves multiple memory accesses and can be time-consuming, especially in systems with large page tables.